This invention relates to power switching transistors and more particularly to vertical MOSFETs that have a gate region located in a xe2x80x9ctrenchxe2x80x9d in the semiconductor material.
MOSFET semiconductor devices in which the gate is formed in a vertically oriented groove in the semiconductor material so that current flow is substantially vertical, have been studied recently by several workers in the field. Ueda, Takagi and Kano, in IEEE Trans. on Electron Devices, Vol. ED-32 (1985) 2-6, have studied the formation of vertically oriented rectangular grooves by a reactive ion beam etching technique, where the structure manifests reduced on-resistance and high cell packing density. Chang and co-workers, in a series of papers, have also studied formation of vertically oriented rectangular grooves, produced by photolithographic techniques, in semiconductor material and self-alignment of the groove boundaries. See, for example, H.R. Chang, et al., IEEE Trans. on Electron Devices, Vol. ED-34 (1987) 2329-2334 and references cited therein; Blanchard, in U.S. Pat. No. 4,767,722, discloses a method for making vertical channel DMOS structures including the use of a vertically oriented rectangular groove filled with doped polysilicon that serves as a gate.
In another research direction, Marcus, Wilson and co-workers have discussed the effects of oxidization on curved silicon surfaces of various shapes, including right angle corners and cylinders and cylindrical cavities. See, for example, Marcus and Sheng, Jour. Electrochemical Soc., Vol. 129 (1982) 1278-1282; Wilson and Marcus, Jour. Electrochemical Soc., Vol. 134 (1987). See also Yamabe and Imai, IEEE Trans. on Electron Devices, Vol. ED-34 (1987) 1681-1687.
Lidow and Herman, in U.S. Pat. Nos. 4,593,302 and 4,680,853, disclose the fabrication of planar power MOSFETs having hexagonally shaped source cells with hexagonally shaped channels being formed beneath the source region in the semiconductor material.
This invention provides an optimized version of a power metal-oxide-semiconductor field-effect transistor (MOSFET) that has the gate region positioned in a vertically oriented groove or xe2x80x9ctrenchxe2x80x9d that extends from the top surface of the structure downward, using a three-dimensional cell geometry that maximizes the gate dielectric breakdown voltage and also provides position of voltage breakdown initiation to allow use of controlled bulk semiconductor breakdown. Bulk breakdown is achieved by using a two-dimensional, field shaping, dopant profile that includes a central deep p+ (or n+) layer that is laterally adjacent to a p body layer and that is vertically adjacent to an epitaxial layer of appropriate thickness and a gate dielectric of appropriate thickness in a trench.
These objects may be realized in accordance with this invention by apparatus that includes:
A substrate of first conductivity type, a first covering layer of first conductivity type lying on the substrate, a second covering layer of second conductivity type lying on the first covering layer and having a bottom surface, and a third covering layer of heavily doped first conductivity type having a top surface and partly lying over the second covering layer, where a portion of the second covering layer is heavily doped and extends vertically upward through a portion of the third covering layer to the top surface of the third covering layer. The apparatus also includes a trench having a bottom surface and side surfaces and extending downward from the top surface of the third covering layer, through the third and second covering layers and through a portion of the first covering layer, where the bottom surface of the trench lies above a lowest part of the, bottom surface of the second covering layer. Electrically conducting material is positioned in the trench, and an oxide layer is positioned between this electrically conducting material and the trench bottom and side surfaces. Finally, three electrodes are attached to the electrically conducting material, to the third covering layer, and to the substrate, respectively. This apparatus allows the transistor to avoid initiation of avalanche breakdown adjacent to the trench.